It is known in the related art to provide an interface unit, such as is shown in FIG. 3, to process analog input signals 2 and to apply a digitized version 4 of selected portions of the analog input signals to a digital system bus. The interface unit 10 can include a plurality of sample-and-hold circuits 11 for monitoring the analog input signals 2 and at controllable times storing the value of the signal then present. A multiplexer unit 12, under control of an address signal 6 can select one of the output signals from the sample-and-hold circuits 11.
The signal from the selected sample-and-hold circuit is applied to an analog-to-digital converter 13. The output signal from the analog-to-digital converter is then coupled to the system bus 3, in response to one or more control signals from the data processing unit 5 (typically a microprocessor) via line 15. The signals on the system bus 3 can be stored in memory unit 8 or can be applied directly to data processing unit 5. In either case, the data processing unit 5 can process the converted digital signals according to a program controlling the data processing unit 5.
In the prior art system shown in FIG. 3, the control signals necessary to control the operation of units 11, 12, and 13 are generated by control logic 14 and typically include the following: a signal to place sample-and-hold circuits 11 in the sample-and-hold mode at the correct time and for the correct duration; address signals to select a particular channel of the multiplexer 12; a signal for the analog-to-digital converter 13 each time a new sample is to be digitized; and a signal for the processor 5 to couple the output signals of the analog-to-digital converter 13 to the system bus 3.
In order to obtain the control signals shown in FIG. 3, two approaches have been utilized in prior art circuits, both of which utilize some form of electronic hardware to generate the necessary control signals.
Referring to FIG. 4A, the operation of an interface unit under synchronous hardware control is shown. A clock 21 associated with the interface unit activates a plurality of counter/timer circuits in unit 22. The counter/timer unit 22 provides a pattern of output signals that can be applied to decoding unit 23. The decoding unit processes the pattern of signals from the counter/timer unit 22 and provides the appropriate control signals to control the interface unit in a pre-established fashion.
FIG. 4B shows a similar prior art circuit for providing control signals in an asynchronous environment. The asynchronous timing circuit 24 (typically composed of random logic circuits such as monostable multivibrators and similar logic components) applies signals to decoding unit 25. The decoding unit 25 has the appropriate logic components to provide the control signals to control the functions of the other components of the interface unit (not shown).
In either of the above-described synchronous or asynchronous configurations, the mechanism providing the control signals comprises electronic hardware located within the interface unit, and once the circuit configuration is established the control signals are fixed and cannot easily be changed.
There has therefore existed an urgent need for an interface between analog input signals and a digital data processing unit system bus that permits the interface unit to respond to control signals from the data processing unit, which control signals establish the operating conditions of the interface unit.